The present invention concerns a charge pumping circuit (e.g. voltage multiplier or voltage booster), which is provided with an innovative arrangement for stabilizing its output voltage.
Often in electronic systems there is a need of generating a DC voltage higher than the supply voltage. Such a voltage boosting function is commonly effected with a so-called voltage multiplier or voltage booster. However, the circuit implementations of a voltage booster may be differ considerably depending on the level of the current that the circuit should be able to deliver.
For relatively low output current levels (in the order of 10 .mu.A), as in the case of write operations of EPROM memories, an often used solution is the circuit shown in FIG. 1a (employing bipolar junction transistors BJT) or in FIG. 1b (employing MOS transistors), as described in Witters et al., "Analysis and Modelling of On-Chip High-Voltage Generator Circuits for Use in EEPROM Circuits", 24 IEEE JOURNAL OF SOLID-STATE CIRCUITS 1372 (October 1989), which is hereby incorporated by reference.
Conversely, when the voltage multiplier must deliver output currents of a remarkable level (in the order of ten mA), as in the case of analog integrated circuits wherein the supply voltage must be doubled or tripled for attaining certain performances, a typical solution requires the employment of at least two large capacitances (normally external to the integration circuit). A first capacitor C.sub.1 is used for loading and transfering electric charge, while the second capacitor C.sub.2 has the function of storing the periodically transferred charge, as schematically depicted in FIG. 2. The four switches (SW1, SW2, SW3, SW4) are driven by first and second phase control signals (.phi..sub.1 and .phi..sub.2).
Basically, during a first phase (.phi..sub.1) of the control clock, the capacitance C.sub.1 is connected between V.sub.CC and ground (GND) and therefore a voltage equal to V.sub.CC develops on the "upper" terminal as referred to the "lower" terminal of the capacitor that is connected to ground. During a second phase (.phi..sub.2) of the control clock, the lower terminal is connected to V.sub.CC while the upper terminal is connected to the output node (on C.sub.2), onto which a voltage V.sub.sur develops.
If the output current is null, then it is easy to see that, after several clock periods, the output voltage V.sub.sur would become equal to 2 V.sub.CC and perfectly stable. The output capacitance C.sub.2 stores the output voltage V.sub.sur.
When a load connected to the output node (V.sub.sur) draws current, the resulting value of the output voltage V.sub.sur will be determined by the balance between the current drawn by the load and the quantity of charge per unit time delivered through the transfer capacitance C.sub.1, while the output capacitance C.sub.2 limits the amplitude of the "ripple" of the output voltage V.sub.su r.
In Callias et al., "A Set of Four IC's in CMOS Technology for a Programmable Hearing Aid", 24 IEEE JOURNAL OF SOLID-STATE CIRCUITS 301 (April 1989), which is hereby incorporated by reference, it is explained that the value of the output voltage V.sub.sur in case of current absorption by a load, may be easily calculated by analyzing the equivalent circuit shown in FIG. 3..sup.1 By following such a derivation, the value of the output voltage in the circuit of FIG. 2 may be seen to be given by the following relationship: FNT .sup.1 By adding more and more stages, it is possible to attain higher multiplication factors, while maintaining a single storing capacitance C.sub.2 connected between the output node (V.sub.sur) and ground (GND). For example, Callias et al. point out that, if it is desired to triple the voltage V.sub.CC, it is sufficient to employ two capacitances C.sub.1a and C.sub.1b (in addition to the capacitor C.sub.2). During the phase .phi.1, capacitances C.sub.1a and C.sub.1b would both charge to V.sub.CC, while during the successive phase .phi.2, capacitances C.sub.1a and C.sub.1b would be connected in series (that is with the lower terminal of the first of the two capacitances C.sub.1a connected to V.sub.CC and the upper terminal of the second capacitor C.sub.1b connected to V.sub.sur) between V.sub.CC and the output node. EQU V.sub.sur =2 V.sub.CC -(R.sub.C1 +R.sub..tau.)I.sub.L
where R.sub.C1 and R.sub..tau. are respectively given by the following equations: ##EQU1## where C.sub.A is the capacitance of C.sub.1 and C.sub.2 in series, and t.sub.1 and t.sub.2 are RC time constants: ##EQU2## In the equations above, f.sub.S is the switching frequency of the control clock, and the r.sub.ON values represent the respective internal resistance of the switches SW1, SW2, SW3 and SW4, that are employed in the circuit. As may be easily observed, the effective value of the output voltage V.sub.sur depends strongly not only on the current I.sub.L absorbed by the load and the value of the supply voltage V.sub.CC, but also on the internal resistances r.sub.ON of the transistors that implement the switches SW1, SW2, SW3 and SW4, that drive the circuit.
The on-resistance of a transistor is an intrinsic parameter which is notoriously dependent from the fabrication process, temperature, supply voltage, etc. Many high precision analog circuits cannot tolerate an excessive spread of the actual output voltage (V.sub.sur) from the design value.
Thus, a main object of the present invention is to provide a simple low-power voltage multiplier or voltage booster, designed for a relatively high output current, the output voltage of which is stable and substantially independent from process spread, temperature, supply voltage and, within certain limits, also from the output current that is actually delivered to a load.
This object and other advantages are achieved by the output voltage stabilizing circuit of the present invention. The circuit of the invention employs an integrating stage, capable of generating a DC error signal, representative of the difference between a reference voltage and the output voltage of the voltage multiplier. The error signal is employed for driving (during a conduction phase of the operating cycle of the multiplier) a transistor that acts as a switch for connecting to ground at least a charge transfer capacitance (C.sub.1) of the voltage multiplier. The generated error signal effectively controls the internal resistance r.sub.ON, so as to keep constant the output voltage V.sub.sur of the voltage multiplier.
Such a driving error signal is fed to a control terminal of the transistor (switch) that connects to ground the charge transfer capacitance of at least a stage of the voltage multiplier, under control of a pair of timing signals, which control a transfer gate of the signal and an auxiliary switch for discharging the control node of the transistor (switch) driven by the error signal.
In the preferred CMOS implementation, PMOS transistors are used to connect the upper terminal of the charge transfer capacitor alternately to the positive supply voltage Vcc and the pumped voltage Vsur, and overdriven clock voltages are used to assure reliable turn-off of these transistors.
Some attempts have been made to provide regulation of a pumped voltage. European application EP-A-0540948 of Zavaleta (Motorola) uses a feedback loop to act on the r.sub.ON of a MOS transistor for regulating the output of the charge pump at the desired value. However, the presently preferred embodiment of the present application provides advantages over the Motorola circuit in the manner of implementing the feedback loop. As may be observed from FIG. 4 of the Motorola application, the circuit that implements a proportional+integral function is very complex. It uses three amplifiers (120, 130 and 142), three capacitances (137, 135 and 139), and several switches. By contrast, the innovative circuit disclosed in the present application provides a very simple structure composed of a single amplifier, a capacitance and a resistance for implementing the same function.
Moreover, since the Motorola circuit separates the proportional function from the integral function pair, they are obliged to drive two PMOS transistors (150 and 151) in order to vary the r.sub.ON ; but in the present invention the two functions are implemented together, and in the presently preferred embodiment driving a single n-channel MOS suffices.
Last but not least, given that a main objective in battery powered systems is to limit power consumption as much as possible for prolonging the life of the battery, the innovative circuit of the presently preferred embodiment consumes much less current (power) than the Motorola's circuit. The disclosed circuit employs a single amplifier directly powered by the battery, while Motorola utilizes three amplifiers, of which at least two (120 and 142) are powered at high (boosted) voltage, that is they consume at least five times the current that is consumed in the innovative circuit of the presently preferred embodiment for implementing the feedback loop. In this connection, it should also be noted that the Motorola circuit which generates PTUBBIAS, which biases the n-wells of the PMOS 150, 151, 152 and 154 at the highest potential of VBAT and VDD in order to avoid direct biasing, does not satisfy at all the function that is required at power-up. In fact, by supposing that at power-down VDD=0 V and that therefore PTUBBIAS=VBAT, when leaving the power-down condition, the capacitance 80 will have charged to VBAT during .phi.1 and therefore, during .phi.2, will tend to strongly pull-up the node 72, thus forward biasing the diode from p+ (node 72) to n-well (common to 150, 151 and 152). This could give rise to a sudden current absorption in the order of 10-60 mA from VBAT, unduly degrading the battery.
The improved circuit embodiments of FIGS. 6 and 7 provide an additional protection against a current surge when power is first applied, by including small resistors in series with the wells of the devices which are interposed between Vcc and the pumped node R.sub.sur. Preferably these resistors are formed merely by lateral extensions of the n-well diffusion.
According to certain disclosed innovative embodiments, there is provided: A voltage multiplier circuit, comprising: at least a first charge transfer capacitance and a second output storing capacitance, a first switch, comprising a single transistor, for connecting to ground a first terminal of the first capacitance; the first terminal of the first capacitance being connected to ground only through the first switch; a second switch for connecting a second terminal of the first capacitance to a supply node; a third switch for connecting the first terminal of the first capacitance to the supply node; a fourth switch for connecting the second terminal of the first capacitance to a first terminal of the second capacitance which provides an output node of the voltage multiplier; the second switch being controlled by a first clock phase and the third and fourth switches being controlled by a second clock phase; and further comprising a voltage divider functionally connected between the output node and a ground node of the circuit; a differential amplifier having a noninverting input to which a reference voltage is fed, an inverting input connected to an intermediate node of the voltage divider and to the output of the amplifier through a series comprising an integrating capacitance and a resistance; a first transfer gate, controlled by a first timing signal and by a complementary signal, coincident with the first clock phase, an input of the transfer gate being connected to the output of the amplifier and an output of the transfer gate being connected to a control terminal of the first switch; a fifth switch, controlled by a second timing signal coincident with the second clock phase being functionally connected between the control terminal of the first switch and ground.
According to certain disclosed embodiments, there is also provided: a circuit for stabilizing the output voltage of a voltage multiplier which comprises an integrating stage capable of outputting a DC error signal representative of a difference between a reference voltage and the output voltage; switching means, controlled by a first and second timing signal, for modulating, in accordance with the error signal, the on-resistance of a transistor which functionally connects a charge transfer capacitor of the voltage multiplier to a ground node, during a conduction phase; the charge transfer capacitor being connected to ground, during the conduction phase, only through the transistor.
According to certain disclosed innovative embodiments, there is provided: A voltage multiplier circuit, for obtaining from first and second supply voltages, on an output storing capacitor, a pumped voltage which is not intermediate between the first and second supply voltages, comprising: at least one charge transfer capacitor; a first switch, connected between the second supply voltage and a first terminal of the charge transfer capacitor; a second switch connected between a second terminal of the charge transfer capacitor and the first supply voltage, and connected to be turned on by an active phase of a first clock; a third switch connected between the first terminal of the charge transfer capacitor and the first supply voltage, and connected to be turned on by an active phase of a second clock; a fourth switch connected between the output capacitor and a second terminal of the charge transfer capacitor, and connected to be turned on by an active phase of the second clock; feedback circuitry operatively connected to provide an output which varies in accordance with the deviation of the pumped voltage from a desired target voltage; a transfer gate, connected between the output of the amplifier and a control terminal of the first switch, and connected to be turned on by an active phase of the first clock; a fifth switch, connected between a control terminal of the first switch and the second power supply, and connected to be turned on by an active phase of the second clock; and one or more resistors interconnected with the second and fourth switches to limit transient current between the first power supply voltage and the output capacitor, when power is first applied to the first power supply voltage.
According to certain disclosed innovative embodiments, there is provided: a voltage multiplier circuit, for obtaining from first and second supply voltages, on an output storing capacitor, a pumped voltage which is not intermediate between the first and second supply voltages, comprising: at least one charge transfer capacitor; a first switch, connected between the second supply voltage and a first terminal of the charge transfer capacitor; a second switch connected between a second terminal of the charge transfer capacitor and the first supply voltage, and connected to be turned on by an active phase of a first clock; a third switch connected between the first terminal of the charge transfer capacitor and the first supply voltage, and connected to be turned on by an active phase of a second clock; a fourth switch connected between the output capacitor and a second terminal of the charge transfer capacitor, and connected to be turned on by an active phase of the second clock; a voltage divider operatively connected between the output node and the second supply voltage to provide a divided-down voltage only when enabled by a power-active signal; a differential amplifier having a noninverting input to which a reference voltage is fed, an inverting input connected to receive the divided-down voltage and to the output of the amplifier through a series comprising an integrating capacitance and a resistance; a fifth switch, connected between a control terminal of the first switch and the second power supply, and connected to be turned on by an active phase of the second clock; and one or more resistors interconnected with the second and fourth switches to limit transient current between the first power supply voltage and the output capacitor, when power is first applied to the first power supply voltage.
According to certain disclosed innovative embodiments, there is provided: A voltage multiplier circuit, for obtaining from first and second supply voltages, on an output storing capacitor, a pumped voltage which is not intermediate between the first and second supply voltages, comprising: at least one charge transfer capacitor; a first field-effect transistor, of a first source/drain conductivity type, having a first source/drain region connected to the second supply voltage and a second source/drain region connected to a first terminal of the charge transfer capacitor; a second field-effect transistor, of a second source/drain conductivity type, connected to be turned on by an active phase of a first clock, and having a first source/drain region connected to the first supply voltage, and a second source/drain region connected to a second terminal of the charge transfer capacitor; a third field-effect transistor, of a second source/drain conductivity type, connected to be turned on by an active phase of a second clock, and having a first source/drain region connected to the first supply voltage, and a second source/drain region connected to the first terminal of the charge transfer capacitor; a fourth field-effect transistor, of a second source/drain conductivity type, connected to be turned on by an active phase of the second clock, and having a first source/drain region connected to a second terminal of the charge transfer capacitor, and a second source/drain region connected to the output capacitor; feedback circuitry operatively connected to provide an output which varies in accordance with the deviation of the pumped voltage from a desired target voltage; a transfer gate, connected between the output of the amplifier and a control terminal of the first switch, and connected to be turned on by an active phase of the first clock; an additional switch, connected between the gate of the first transistor and the second power supply, and connected to be turned on by an active phase of the second clock; the second and fourth transistors each having a resistive connection between the respective second source/drain region thereof and a respective body region thereof.
According to certain disclosed innovative embodiments, there is provided: a charge pump circuit, for obtaining, from positive and zero supply voltages, a negative voltage on an output storing capacitor, comprising: at least one charge transfer capacitor; a first field-effect transistor, having a first P-type source/drain region connected to the positive supply voltage and a second P-type source/drain region connected to a first terminal of the charge transfer capacitor; a second field-effect transistor, connected to be turned on by an active phase of a first clock, and having a first N-type source/drain region connected to the first supply voltage, and a second source/drain region connected to a second terminal of the charge transfer capacitor; a third field-effect transistor, of a second source/drain conductivity type, connected to be turned on by an active phase of a second clock, and having a first source/drain region connected to the first supply voltage, and a second source/drain region connected to the first terminal of the charge transfer capacitor; a fourth field-effect transistor, of a second source/drain conductivity type, connected to be turned on by an active phase of the second clock, and having a first source/drain region connected to a second terminal of the charge transfer capacitor, and a second source/drain region connected to the output capacitor; feedback circuitry operatively connected to provide an output which varies in accordance with the deviation of the pumped voltage from a desired target voltage; a transfer gate, connected between the output of the amplifier and a control terminal of the first switch, and connected to be turned on by an active phase of the first clock; an additional switch, connected between the gate of the first transistor and the second power supply, and connected to be turned on by an active phase of the second clock; the second and fourth transistors each having a resistive connection between the respective second source/drain region thereof and a respective body region thereof.
According to certain disclosed innovative embodiments, there is provided: an integrated circuit method for generating from first and second supply voltages, using at least one charge transfer capacitor, a pumped voltage, on an output storing capacitor, which is not intermediate between the first and second supply voltages, comprising the steps of: on a first clock phase, connecting a first terminal of the charge transfer capacitor to the first supply voltage, and connecting a second terminal of the charge transfer capacitor to the second supply voltage, using at least one variable impedance element which is regulated in accordance with variations of the pumped voltage from a target voltage; on a second clock phase which does not overlap with the first clock phase, connecting the second terminal of the charge transfer capacitor to the first supply voltage, and connecting the first terminal of the charge transfer capacitor to provide the pumped voltage on the output storing capacitor; the steps (a.) and (b.) being repeatedly alternated; and when power is first applied, routing at least some of the transient current between the first power supply and the output storing capacitor through one or more series resistors.